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Sheet目录3875

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2007 Microchip Technology Inc.

Preliminary

DS70165E-page 91

dsPIC33F

6.3

Interrupt Control and Status

Registers

dsPIC33F devices implement a total of 30 registers for

the interrupt controller:

INTCON1

INTCON2

IFS0 through IFS4

IEC0 through IEC4

IPC0 through IPC17

INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit as well as the control

and status flags for the processor trap sources. The

INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a Status bit, which is

set by the respective peripherals or external signal and

is cleared via software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

The INTTREG register contains the associated inter-

rupt vector number and the new CPU interrupt priority

level, which are latched into vector number (VEC-

NUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in

the INTTREG register. The new interrupt priority level

is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 6-1. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP

bits in the first position of IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register, SR, contains the IPL<2:0> bits

(SR<7:5>). These bits indicate the current CPU inter-

rupt priority level. The user can change the current

CPU priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit which,

together with IPL<2:0>, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

All Interrupt registers are described in Register 6-1

through Register 6-32, in the following pages.

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